Frequency divide circuits are found in numerous applications. They play an integral part, in particular, when used in connection with radio frequency (RF) synthesizer techniques. The majority of frequency dividers are realized digitally by the use of edge triggered flip-flops, while the remainder are realized as analog circuits based on varactor diodes and resonant circuits.
Digital divider circuits based upon edge triggering are designed by configuring a flip-flop to change state on a rising or a falling edge, but not on both. This constitutes, in effect, a divide-by-2 circuit. A divide-by-2.sup.n circuit (i.e. one having a divide ratio N=2.sup.n =2, 4, 8, etc.) is made by cascading the desired number of flip-flops. If the goal is a non-2.sup.n divide ratio (i.e. N=3, 5, 6, 7, etc.), a feedback circuit between flip-flops can be used, and there are many ways to do this. Both off-the-shelf, pre-designed dividers with fixed divide ratios and dividers custom constructed by the equipment designer using the industry-standard 4-bit counter are built on this technique.
For example, Plessey Semiconductor currently offers the most comprehensive selection of pre-designed dividers, all constructed of silicon. The following are representative of the highest input frequency, odd ratio dividers currently offered for N&lt;10: the SP8720 divides by 3 at a maximum input frequency F.sub.max =300 MHz; the SP8620 divides by 5 at F.sub.max =400 MHz; the SP8740 divides by 6 or 7 at F.sub.max =300 MHz; and the SP8743 divides by 9 at F.sub.max =500 MHz.
Gigabit Logic currently offers the highest non-2.sup.n divider, the 10G070, which is a 2.0 GHz dual-modulus divider. However, it divides by 5 or 6 only. To divide by 3, 5, 6, 7 or 9, the above identified products of Plessey Semiconductor or Gigabit Logic are the options.
For custom designs in the digital category, the 4-bit programmable counter with ripple count output, enable input, asynchronous clear and preset terminals readily lends itself to 2.sup.n and non-2.sup.n frequency division. This device is available in CMOS, TTL, ECL and Gallium Arsenide (GaAs) circuit technologies. CMOS and TTL counters, which many companies manufacture, have maximum input frequencies at about 100 MHz. Motorola, for example, makes an ECL counter (the MC10H016) with a 200 MHz maximum input frequency. Gigabit Logic makes a GaAs counter (the 10G061) with a 1.3 GHz maximum input frequency. However, due to propagation delays, feedback circuits inherently reduce maximum input frequencies, often by a multiplicative factor of 0.60 to 0.80, compared to the same flip-flops configured for straight 2.sup.n divide ratios with no feedback.
As for the analog option, such frequency divider circuits are based on, and designed with, varactor diodes and are not widely used or available. This may be for the following reasons: the non-2.sup.n divide ratio devices (limited to N=3) generate many high-level spurs and subharmonics; they are easily prone to isolation; and they have a very small input RF power range beyond which they are unstable. These characteristics have been discovered from measurements made on an analog divide-by-3 circuit.
In view of the above, it can be concluded that the only prepackaged divider above 500 megahertz (MHz) input frequency is limited to divide ratios of 5 and 6, and the maximum input frequency of a 4-bit counter set for a non-2.sup.n divide ratio is 1 GHz.
Thus, while there are many multi-GHz input 2.sup.n dividers, i.e. with a divide ratio N=2, 4, 8, 16, etc., frequency dividers are not currently available for dividing a high input frequency by a non-2.sup.n number.
Various prior art patents have been directed to frequency division. Among those of interest are the following.
In U.S. Pat. No. 4,651,334 (Hayashi), a variable divider that uses a transmission delay to determine a frequency division number is disclosed. Various factors that are included in a time delay feedback loop, which also is connected between a Qbar output to a Reset (clear) input of a D flip-flop integrated circuit. Two D flip-flops are used in the disclosed circuit.
In U.S. Pat. No. 4,845,727 (Murray), a divider circuit is disclosed that uses two D flip-flops where the output of the first flip-flop is fed into the input of the second, and the Qbar output of the second flip-flop is used to drive the first flip-flop via a feedback circuit. The feedback circuit described is placed between the Qbar output and the CLR input of only one of the D flip-flops.
In U.S. Pat. No. 4,730,349 (Wilhelm, et al.), a wideband frequency divider is disclosed that uses two D flip-flops with a feedback loop comprising a memory circuit. The two flip-flops used are connected in a master-slave relationship.
In U.S. Pat. No. 4,715,052 (Stambaugh), a frequency divide-by-N circuit is disclosed where the division is accomplished by use of shift registers to provide an output of f/n. The circuit described does not incorporate the use of D flip-flops, but does display the ability to generate a divide-by-N circuit where N is an odd number.
In U.S. Pat. No. 4,688,237 (Brault), a device for use as a frequency divider in generating clock signals is disclosed. General background information for generating clock signals at a fractional frequency of a reference frequency is also disclosed.
In U.S. Pat. No. 3,873,815 (Summers), a circuit is disclosed for providing a frequency division by an odd integer. Also disclosed is the use of a single D flip-flop as a frequency divider having the ability to divide by an odd integer where n.ltoreq.5 and two D flip-flops where n&gt;5. The patent describes use of a binary counter in the feedback circuit of the D flip-flop. The Qbar output of the flip-flop is not directly fed back in the described divider circuit.
In U.S. Pat. No. 4,366,394 (Clendening et al.) use of a master-slave D flip-flop combination is disclosed that uses the Qbar output connected as a feedback loop to the reset (clear) of the first D flip-flop. The signal fed back is first passed through a NOR gate and then is delivered to the reset input. The feedback circuit includes logic processing, and also two D flip-flops are used for the divide-by-3 capability of the described circuit.